1. Field of the Invention
Embodiments of the invention relate generally to nonvolatile semiconductor memory systems. More particularly, embodiments of the invention relate to nonvolatile semiconductor memory systems including multi-level nonvolatile memory cells and methods for programming the multi-level nonvolatile memory cells.
2. Description of Related Art
Nonvolatile memory systems are commonly employed in a wide variety of consumer and industrial electronic applications. Common examples of such applications include cellular telephones, personal digital assistants (PDAs), MP3 players, digital cameras, portable disk drives, portable media players (PMPs), and auxiliary memories such as the basic input/output system (BIOS) for personal computers, to name but a few.
Due to the widespread use of nonvolatile memory systems, there continues to be an increasing demand for nonvolatile memory systems having higher data storage capacity and higher overall performance. As a result, researchers are continually striving to find new ways to store more data per memory chip unit area within nonvolatile memory systems.
The use of multi-level nonvolatile memory cells is one technique that has been adopted to increase the amount of stored data per unit memory chip area in nonvolatile memory systems. A multi-level nonvolatile memory cell is a capable of storing more than one bit of data. Accordingly, multi-level nonvolatile memory cells are often interchangeably referred to as multi-bit nonvolatile memory cells.
A typical example of a multi-level nonvolatile memory cell is a multi-level flash memory cell. In general, flash memory cells store data in relation to distinct threshold voltage distributions. In other words, when a different data value is programmed within a flash memory cell, the threshold voltage of the flash memory cell changes from within one threshold voltage distribution to within another threshold voltage distribution.
For instance, (FIG.) 1 illustrates two distinct threshold voltage distributions used to store data in a single level flash memory cell. In the example of FIG. 1, where the single level flash memory cell has a threshold voltage within a threshold voltage distribution labeled “1”, the single level flash memory cell stores a logical “1”. Otherwise, where the single level flash memory cell has a threshold voltage within a threshold voltage distribution labeled “0”, the single level flash memory cell stores a logical “0”. Accordingly, the logic state of single bit stored in the single level flash memory cell can be determined by applying a read voltage Vread to a control gate of the single level flash memory cell and determining whether the threshold voltage of the single level flash memory cell is above or below read voltage Vread.
Similarly, FIG. 2 illustrates four distinct threshold voltage distributions used to store data in a multi-level flash memory cell. In particular, the multi-level flash memory cell of FIG. 2 is capable of storing two bits of data, as indicated by the labels on the four threshold voltage distributions. In other words, where the multi-level flash memory cell of FIG. 2 has a threshold voltage within a threshold voltage distribution labeled “11”, the multi-level flash memory cell stores a logical “11” (i.e., most significant bit (MSB) “1” and least significant bit (LSB) “1”), where the multi-level flash memory cell has a threshold voltage within a threshold voltage distribution labeled “10”, the multi-level flash memory cell stores a logical “10”, where the multi-level flash memory cell has a threshold voltage within a threshold voltage distribution labeled “01”, the multi-level flash memory cell stores a logical “01”, and where the multi-level flash memory cell has a threshold voltage within a threshold voltage distribution labeled “00”, the multi-level flash memory cell stores a logical “00”.
FIG. 3 illustrates an exemplary nonvolatile memory system including a flash memory comprising multi-level flash memory cells.
Referring to FIG. 3, an exemplary nonvolatile memory system 100 comprises a host 110, a memory controller 120, and a flash memory 130. Among other things, memory controller 120 comprises a buffer memory 121 and flash memory 130 comprises a memory cell array 131 and a page buffer 132.
In memory controller 120, buffer memory 121 temporarily stores data to be programmed in flash memory 130 during program operations. Buffer memory 121 also temporarily stores data read from flash memory 130 during read operations. Buffer memory 121 operates under the control of memory controller 120 and transfers data from host 110 and to flash memory 130 during program operations, and transfers data from flash memory 130 and to host 110 during read operations.
In flash memory 130, memory cell array 131 stores programmed data. Page buffer 132 temporarily stores data to be programmed in memory cell array 131 in program operations and data read from memory cell array 131 in read operations. Memory cell array 131 comprises a plurality of multi-bit nonvolatile memory cells arranged in rows and columns. As an example, cell array 131 may comprise a NAND flash memory array including NAND flash memory cells arranged in a plurality of NAND strings. Typically, the columns of memory cell array 131 are connected to corresponding bitlines and the rows are connected to corresponding wordlines.
Each row of multi-bit nonvolatile memory cells connected to the same wordline in memory cell array 131 corresponds to one or more pages of data storage. Typically, though not necessarily, programming and read operations are performed on memory cell array 131 one page at a time. As an example, a page of data to be programmed in memory cell array 131 is first transferred to page buffer 132. Then, appropriate voltages are applied to a wordline and bitlines corresponding to a row of memory cells to be programmed in memory cell array 131, based on the page of data stored in page buffer 132.
Where the memory cells in the row are multi-bit memory cells, each row of nonvolatile memory cells connected to the same wordline in memory cell array 131 will correspond to more than one page of data storage. For instance, a row of 2-bit nonvolatile memory cells will correspond to two pages of data. In particular, the two pages, which can be independently programmed, correspond to a least significant bit (LSB) page and a most significant bit (MSB) page because they correspond to LSB and MSB data of the respective 2-bit memory cells, respectively.
In a program operation of nonvolatile memory system 100, host 110 sends a program command and associated program data to memory controller 120. Memory controller 120 receives the program command and the program data and stores the program data in buffer memory 121. In response to the program command, memory controller 120 then controls flash memory 130 to load the program data from buffer memory 121 into page buffer 132. Memory controller 120 then further controls flash memory 130 to program the program data into selected memory cells of memory cell array 131. The location of the selected memory cells in memory cell array 131 where the program data is programmed is typically specified by a program address provided to memory controller 120 by host 110 together with the program command. Usually, flash memory 130 includes row and column decoders that can be used to select appropriate bitlines and wordlines in memory cell array 131 for the program operation based on the program address.
In a read operation of nonvolatile memory system 100, host 110 sends a read command to memory controller 120. In response to the read command, memory controller 120 controls flash memory 130 to transfer read data stored in selected memory cells of memory cell array 131 to page buffer 132. Memory controller 120 then further controls flash memory 130 to transfer the read data from page buffer 132 to buffer memory 121. Finally, memory controller 120 controls buffer memory 121 to transfer the read data from buffer memory 121 to host 110. Similar to the program operation, the location of the selected memory cells of memory cell array 131 is typically specified by a read address provided to memory controller 120 by host 110 together with the read command. Likewise, flash memory 130 generally uses row and column decoders to select appropriate bitlines and wordlines of memory cell 131 for the read operation based on the read address.
Following a program operation, memory controller 120 typically controls flash memory 130 to perform a program-verify operation. The program-verify operation is similar to a read operation, except that the purpose of the program-verify. operation is to determine whether selected memory cells have been successfully programmed. In the program-verify operation, program-verify data is transferred from selected memory cells that were programmed in the program operation, to page buffer 132. Page buffer 132 temporarily stores the program-verify data and the program verify data is compared to program data still stored in buffer memory 121. Where the program data stored in buffer memory 121 is not the same as the program-verify data in page buffer 132, the selected memory cells have not been successfully programmed. Otherwise, where the program data stored in buffer memory 121 is the same as the program-verify data in page buffer 132, the selected memory cells have been successfully programmed. Where the selected memory cells have not been successfully programmed, these memory cells are then either re-programmed with the program data stored in buffer memory 121 or the program data is programmed in a new location of memory cell array 131, such as a different page or a different block.
FIGS. 4 and 5 illustrate different methods that can be used to program a nonvolatile memory system such as that illustrated in FIG. 3. In particular, the methods of FIGS. 4 and 5 are examples of methods for programming nonvolatile memory systems including 2-bit memory cells. In these and other examples, the correspondence between logic states and threshold voltages can be rearranged. For instance, in FIGS. 4 and 5, logic states are assigned to threshold voltages in a non-gray-coded and gray-coded order, respectively. In addition, the order in which respective bits are programmed can also be varied. For instance, although FIGS. 4 and 5 illustrate programming a LSB before programming a MSB, a MSB could alternatively be programmed before the LSB. Moreover, a variety of other programming variations are known in the art and will therefore not be described in detail.
Referring to FIG. 4, a programmed state of a multi-bit nonvolatile memory cell is characterized in relation to five different threshold voltage distributions. Four of these five threshold voltage distributions correspond to respective logic states “11”, “01”, “10”, and “00”, and one threshold voltage distribution corresponds to an intermediate programming state, denoted by a dotted arc. In this example, logic state “11” corresponds to an erased state of the multi-bit nonvolatile memory cell, and logic states “01”, “10”, and “00” correspond to programmed states of the multi-bit nonvolatile memory cell.
In the method illustrated in FIG. 4, the memory cell is initially in the erased state. From the erased state, a LSB of the memory cell is programmed first, followed by a MSB of the memory cell. In programming the LSB, if the LSB to be programmed in the memory cell is a logical “0”, the method changes the memory cell from logic state “11” to the intermediate programming state, as indicated by an arrow labeled “Program0”. Otherwise, the memory cell remains in logic state “11”. Next in programming the MSB, if the MSB to be programmed in the memory cell is a logical “0”, the method changes the memory cell from the intermediate programming state to logic state “00” as indicated by an arrow labeled “Program1”, or from logic state “11” to logic state “01” as indicated by an arrow labeled “Program3”, depending on the logic state of the LSB. Otherwise, where the MSB to be programmed in the memory cell is a logical “1”, the method changes the memory cell from the intermediate programming state to logic state “10” as indicated by an arrow labeled “Program2”, or maintains the memory cell in logic state “11”, depending on the logic state of the LSB.
Referring to FIG. 5, a programmed state of a multi-bit nonvolatile memory cell is characterized in relation to four different threshold voltage distributions. The four threshold voltage distributions correspond to respective logic states “11”, “10”, “00”, and “01”. In this example, logic state “11” corresponds to an erased state of the multi-bit nonvolatile memory cell, and logic states “10”, “00”, and “01” correspond to programmed states of the multi-bit nonvolatile memory cell.
In the method illustrated in FIG. 5, the memory cell is initially in the erased state. From the erased state, a LSB of the memory cell is programmed first, followed by a MSB of the memory cell. In programming the LSB, if the LSB to be programmed in the memory cell is a logical “0”, the method changes the memory cell from logic state “11” to logic state “10” as indicated by an arrow labeled “Program1”. Otherwise, the memory cell remains in logic state “11”. Next in programming the MSB, if the MSB to be programmed in the memory cell is a logical “0”, the method changes the memory cell from logic state “10” to logic state “00” as indicated by an arrow labeled “Program2”, or from logic state “11” to logic state “01” as indicated by an arrow labeled “Program3”, depending on the logic state of the LSB. Otherwise, if the MSB to be programmed in the memory cell is a logical “1”, the memory cell remains in logic state “10” or logic state “11”, depending on the logic state of the LSB.
In general, when the programming methods illustrated in FIGS. 4 and 5 are performed, the LSB and the MSB of the memory cell will not always be programmed in immediate succession. Instead, for example, the LSB of the memory cell may be programmed first, followed by programming operations for memory cells in different rows of the memory cell array, and then the MSB of the memory cell may be programmed next. Accordingly, the logic state of the LSB must generally be ascertained, e.g., by reading the memory cell before the MSB of the memory cell can be programmed so that the threshold voltage of the memory cell can be changed to within the correct threshold voltage distribution.
Unfortunately, however, if an error or malfunction occurs during programming of the MSB, the LSB may be permanently lost. For instance, if MSB programming is performed on the memory cell as indicated by the arrow labeled “Program3” in FIG. 5 and the MSB programming stops short of threshold voltage distribution corresponding to logic state “01”, it may be impossible to determine, based on a simple inspection of the memory cell, whether the LSB of the memory cell was a logical “1” or a logical “0”. Fortunately, in such cases, the MSB data can generally be recovered from buffer memory 121. However, the loss of the LSB data may ultimately cripple the performance of nonvolatile memory system.
This problem becomes increasingly important as researchers continue striving to fit more and more data storage capacity within a limited chip area of nonvolatile memory devices, because as the integration density of nonvolatile memory chips increases, the likelihood of errors and malfunctions in programming operations tends to increase accordingly. As a result, it would be beneficial to effectively address problems such as the above described data loss problem in multi-level cells caused by programming errors or malfunctions.